(define_insn "and<mode>3<vczle><vczbe>"
  [(set (match_operand:VDQ_I 0 "register_operand" "=w,w")
	(and:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w,0")
		   (match_operand:VDQ_I 2 "aarch64_reg_or_bic_imm" "w,Db")))]
  "TARGET_SIMD"
  "@
   and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>
   * return aarch64_output_simd_mov_immediate (operands[2], <bitsize>,\
					       AARCH64_CHECK_BIC);"
  [(set_attr "type" "neon_logic<q>")]
)